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Well, it does work out to an appreciable amount of power over the course of say, a year, which would guarantee that every group of cell in those particular groups would need to have power bled off by the active circuit. I figure whats 4 extra $0.001 (or less) resistors to just take that out of the equation.
Part of the reasoning behind the BMS is so that in the critical winter months I can operate in a wider SoC window and pack a little more power into the cells safely. So instead of working within say, 10%-90% I can bump that to 7%-93% for the ~30 critical winter days for a little added buffer (in my case ~+10kWh).
I've still debating on surface mount. If I can't get my layout to easily fit with through hole I'll probably just get assembly service done for a full surface mount component based board.
Yeah, I was considering this, but to do over-sampling/decimation with the AVR's 10-bit ADC you basically need it running continuously to get a low overall sample rate that is accurate (about one sample per ~1.5 seconds in practice). In practice you can easily get ~16-bit resolution this way by causing the CPU to generate some somewhat random/white noise or by having just minimal noise on the line to begin with during the ADC process (which seems counter intuitive). The 100nF cap would filter a bit of that noise too and drop my resolution down a bit, so I'm probably going to omit it unless I end up going with a higher resolution ADC in the end.
If I may ask, why 16 bit resolution? 10 bit should be sufficient, 12 bit at worst if you want to match cells a little closer. Guess it's a case of software so no real additional expense except your time?
I've used oversampling with additional noise before to get higher bit resolution, but I found that a lot of the little nonlinearity errors (DNL, INL, gain error etc) contributed enough to reduce the effective bits (ENOB) down to only slightly more than the ADC peripheral specified (IIRC I got something like 12 bits using 16x oversampling from a 10 bit ADC on a PIC16F microcontroller)
I've used oversampling with additional noise before to get higher bit resolution, but I found that a lot of the little nonlinearity errors (DNL, INL, gain error etc) contributed enough to reduce the effective bits (ENOB) down to only slightly more than the ADC peripheral specified (IIRC I got something like 12 bits using 16x oversampling from a 10 bit ADC on a PIC16F microcontroller)
Two ATtiny micros per boad, each one powered by and measuring 3 cells -- so on the board, micro 1 and all associated circuitry is completely isolated from micro 2 and its stuff (12V ground difference) which are both isolated from the "main" serial comm link back to a master data collector device (and therefore isolated from all the other BMS boards, in your case up to 48V ground difference)?
Sounds fun! Just be careful where the multimeter probes go... ;-)
Sounds fun! Just be careful where the multimeter probes go... ;-)
spaceballs
Member
I also made up my own BMS board that fits where the BMB is in the sheet (module) in the Roadster ESS. You can talk to it over isolated rs232 and it has an wifi module on it where it will connect to a access point. It has it's own basic web interface to monitor, charge, move power from one cell to another, get isolated power externally, and also discharge.
Somehow I missed this post! Very impressive. Looks much better than my crazy setup...
Your electronics-fu seems stronger than mine by a long shot. What method did you use for reading individual cell voltages? I couldn't think of a good way to do this with a single AVR chip with accuracy since the AVR references everything to ground when doing ADC measurements, and the reference voltage can't exceed VCC.
My current method is using a calibrated resistor network (using 4.096V reference voltages in place of cells for a software-based calibration session) to measure cell 1, cell1+2, and cell 1+2+3 and do the math to get the individual cell voltages, then isolating that chip from a master for digital comm (currently just to a USB232 adapter using a software UART).I decided on just three cells at a time since errors accumulate with each cell added with this method. No charge shuttling or anything, just bleed resistors behind some transistors so they feed off the right cell.
I've been able to get accuracy to ~ +/- 4mV reading cell voltages with my breadboard disaster of a prototype sub-BMB, as well as ~120mA balancing circuits for each cell.
I switched to the ATTiny24 since I'm an idiot and forgot I'd need pins to activate the balancing circuits.
This whole mess draws a few dozen mW, including the isolation IC, from the three cell group. An issue with this setup is the mA or so need to activate the transistor for the bleed resistor is spread across the three cells. So, I'll have to pulse the bleed resistors on the other 9 cell-sets in that group (in my setup that has 12 cells in series) with a calculated duty cycle to make sure that they stay in line. Definitely not the most efficient, but I think it will work for me.I need to get the a master chip going so that I'm not doing floating point math on a 2KB MCU for debug purposes... lol.
Definitely open to improvement suggestions. (Buy a BMS is not a valid suggestion.
)Ran my test design using three 4.096V reference voltage generators in series for ~12 hours. After calibration (which I'll automate later) readings didn't even drift 1mV.
I was planning on just calibrating each board individually once, but I may just include a 4.096V reference IC on each board and tie it to an extra ADC pin on the AVR to continuously calibrate things, but at that point I should probably just use the 4.096V as the ADC reference vs the internal 1.1V reference and it would add several dollars to each board. So probably just going to stick with external one-time calibration. Maybe if I do decide to use an inexpensive 5V reference IC as power for the AVR (like I am in testing) I'll just tie that to an ADC pin as a sanity check.
I was planning on just calibrating each board individually once, but I may just include a 4.096V reference IC on each board and tie it to an extra ADC pin on the AVR to continuously calibrate things, but at that point I should probably just use the 4.096V as the ADC reference vs the internal 1.1V reference and it would add several dollars to each board. So probably just going to stick with external one-time calibration. Maybe if I do decide to use an inexpensive 5V reference IC as power for the AVR (like I am in testing) I'll just tie that to an ADC pin as a sanity check.
I know just barely enough to be suitably impressed.
Ran my test design using three 4.096V reference voltage generators in series for ~12 hours. After calibration (which I'll automate later) readings didn't even drift 1mV.
Nice!
spaceballs
Member
Over the shelf part designed for BMS systems. LTC6802IG-2#PBF Linear Technology | LTC6802IG-2#PBF-ND | DigiKey
I just read the voltage data from that chip.
This is an old problem but now a days nonissue due to cheap voltage stack monitoring ICs https://www.google.com/url?sa=t&rct...luo1x-52A&sig2=E_43hIJEPfZVefowOsbFeg&cad=rja
Curious is the AVRs how are they going to be powered? off one group of cells or the entire module? Also what will you use for voltage regulation to the AVRs.
Your approach looks good to me.
Understandable!
Well, considering my prototype is getting more complicated by the day, I may scrap the idea and look into these further. I just figured it'd be fun to try and use a bunch of stuff I had on hand, like the AVRs.
I've been testing a few ideas for this. As of right now, each 3-cell AVR + isolation group will run from those three cells at the ~9-12V level of input. The setup is so low power that the method that's working well in my prototyping has been a TO-92 5V voltage reference IC. Virtually no efficiency loss at these tiny current levels (few mA), requires no external components, and is a super stable output voltage that is helpful for the AVR's internal reference voltage staying stable during conversions. For the main AVR on the BMB's they will be powered from a central source derived from the entire pack, and a simple buck converter on each BMB probably so that I can put 48V through the daisy chained interconnects at super low currents with little loss.
Thanks.
It is likely not going to be as efficient as it could be using something like a premade BMS IC, but it's definitely more fun. Putting some of the components I have in my stock to good work is a plus, too. I estimate, based on the current prototype, that the BMS in total will use something like 10 kWh/year, not counting bleed resistor usage. For a setup like mine that produces 10 kWh in 15 minutes I don't think this is going to be an issue. While I do plan on open sourcing this project for others once I have a full working version, I presently don't intend to market it, and others are welcome to improve the efficiency if they so desire. I think having a drop in replacement for Tesla's BMB's is going to be pretty valuable once more of these packs start ending up in the wild and people try to repurpose them.
I'm also working on reading the bi-directional low-side 500A/50mV current shunts that I have installed in each inverter's load center as part of the full BMS setup. Definitely am going to use an IC designed for this, then feed that to an AVR, since there are 8 of them and I want it as accurate as possible. All power to and from the pack will go through one of these shunts, so summing them up will give me the exact power draw or push of the full pack. This way I can more accurately dial in the output of the charge controllers once the pack is to my full set point while maintaining PV output to offset loads 100%.
wk057 is banned from posting. He does not want to abandon the discussion of this project. People interested in following the project may do so here: http://wk057.solar/
Been a while since I updated this thread.
Here is a 3D render of my terribly laid out prototype PCB for this project (inner two layers not visible). I has finished my schematic, but not routing, when my friend said he needed any board prototypes that I wanted printed ASAP if I wanted them done soon (next window not until the end of the month). So I should be getting a few of these boards this weekend. I'm kind of ashamed of the armature routing and placement job, but I didn't have time to clean it up.
I did end up going to with some surface mount components. Basically things I can hand solder. No stencils or anything. Again, this is far from a production version of such a design, but I think it will serve my purposes after a few revisions. Basically just need a proof of concept of my custom data bus and chaining method without having to solder 1000 wires on perf board.
In testing with my latest perf board prototype I was able to achieve cell voltage reading accuracy of +/- 2mV for the six test cell set. I purposely threw a few of my test cells out of balance to test the balancing circuitry, and it worked well. Since I was testing with just one cell per cell group the board was able to correct a pretty gross imbalance in just a few hours. In the full pack it could potentially take days or weeks to correct a large imbalance, but I don't expect to have a large imbalance in the real setup unless there is a problem.
More to come.
Here is a 3D render of my terribly laid out prototype PCB for this project (inner two layers not visible). I has finished my schematic, but not routing, when my friend said he needed any board prototypes that I wanted printed ASAP if I wanted them done soon (next window not until the end of the month). So I should be getting a few of these boards this weekend. I'm kind of ashamed of the armature routing and placement job, but I didn't have time to clean it up.
I did end up going to with some surface mount components. Basically things I can hand solder. No stencils or anything. Again, this is far from a production version of such a design, but I think it will serve my purposes after a few revisions. Basically just need a proof of concept of my custom data bus and chaining method without having to solder 1000 wires on perf board.
In testing with my latest perf board prototype I was able to achieve cell voltage reading accuracy of +/- 2mV for the six test cell set. I purposely threw a few of my test cells out of balance to test the balancing circuitry, and it worked well. Since I was testing with just one cell per cell group the board was able to correct a pretty gross imbalance in just a few hours. In the full pack it could potentially take days or weeks to correct a large imbalance, but I don't expect to have a large imbalance in the real setup unless there is a problem.
More to come.
spaceballs
Member
Question on C10 I assume that is a crystal, where is your caps on either side of the crystal?
Shouldn't be ashamed as long as it passes DRC checks, also you can clean up the layout on your next revision since you will have more time. btw when you do your low volume run I recently tried this guys with good success Imagineering - Printed Circuit Board Fabrication - Home
C10 is just a 0.1uF cap. Using the internal 8 MHz oscillator for that AVR. I guess placement does make it look like a crystal.
Yeah, DRC passed. But I usually like to take the time to make my PCBs look neat. I don't get them done too often, so it's nice to put in the extra effort to make them look clean in case I end up using them beyond the prototype phase, which has happened. Looking over this board again and I found a few small errors that are correctable, and fortunately the inner layers look good. I want to test this one out before I make any major revisions to the layout and routing though.
As for printing, I can't beat the deal I have currently, which is next to $0 for small quantities as long as I can work with getting designs over nearly on-demand as space is available and I don't care what color my solder mask or silkscreen is.
Currently the stock BMBs seem to be doing some amount of balancing on their own. However they aren't networked together anymore, so they're not going to be very effective on the whole. Plus I was never able to figure out how to interface with the stock BMBs despite a good amount of effort along with begging Tesla for some specs.
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